Wednesday, August 29, 2012

MPC89E54 Crack

STC's STC89 and STC12 series are produced by Megawin, pasted and sold by Shenzhen Hongjing. The Megawin's MPC89E series microcontrollers can be completely compatible instead of STC89 Series MCU, MPC82 series of microcontrollers can be fully compatible instead of STC12 Series MCU, which means you can replace the STC MCU.We offer the full range of Megawin MCU crack service.
MPC89E51   MPC89E52   MPC89E53   MPC89E54   MPC89E58   MPC89E515
MPC89LE51  MPC89LE52  MPC89LE53  MPC89LE54  MPC89LE58  MPC89LE515
MPC82E52   MPC82E54   MPC82LE52  MPC82LE54

Wednesday, August 15, 2012

TMS320 DSP Standard Interface for Negotiating DMA Resources

TMS320 DSP Standard Interface for Negotiating DMA Resources

TMS320 DSP Algorithm Standard (xDAIS) compliant algorithms designed for the ‘C64x+ EDMA3 controller must implement the IDMA3 interface to publish and acquire DMA resources they will use. The application framework DMA Resource Manager (DMAN3 is one reference implementation provided by the Framework Components) calls IDMA3 interface functions to query and subsequently allocate and grant the requested DMA resources. The IDMA3 interface is similar to the xDAIS IDMA2 interface in terms of its definition and role. IDMA3 introduces the notion of a logical DMA channels abstraction via a handle similar to that used in IDMA2.

DMA Transfer Configuration Settings

 DMA Transfer Configuration Settings

The purpose of acquiring logical channel handles is to submit DMA transfer requests. Each submitted DMA transfer request specifies a source and destination memory region. A background DMA activity asynchronously carries out the copying of the contents of the source memory region to the destination.

The configuration setting of a logical channel is similar to the hardware register settings of the underlying EDMA3.0 hardware DMA device. However, each logical channel retains its configured DMA transfer settings. The most recently configured transfer settings at the time the ACPY3_start function is called apply to the asynchronously started DMA transfer.

Two properties of DMA transfers make them desirable and performance critical for algorithms:

    The physical transfer/copy operation takes place in the “background” under the close control of specialized circuitry and controllers. This allows algorithms to issue transfer requests in advance and to perform other useful operations while data is being copied in the background.
    The physical layout of source or destination DMA transfer blocks need not be a single contiguous chunk of memory. By setting a few channel configuration parameters, algorithms can specify complex layout patterns. This can lead to significant performance improvements even if the algorithm cannot take advantage of asynchronous execution and the CPU sits idle while waiting for the transfer to complete.

The unit of DMA transfer is a block composed of frames and elements. Each DMA transfer is submitted on a logical channel via the ACPY3_start function. The source and destination addresses for the blocks and the number of elements in each frame are now part of the channel’s configuration settings. The configuration parameters are intrinsic properties of each logical channel and are set exclusively when the algorithm calls ACPY3 configuration functions. The previously configured properties of each logical channel at the time of an ACPY3_start request determine the actual memory copied from source to destination. Each DMA transfer is characterized by the following list configurable attributes. (Figure 2 illustrates the memory layout of a DMA transfer block characterized by these configuration parameters). Note that the element and frame index parameters can be configured independently for both source and destination.

    transferType. 1D-to-1D, 1D-to-2D, 2D-to-1D or 2D-to-2D
    elementSize. The number of 8-bit bytes per element. The element size for ACPY3 transfers can be a variable number, 1 <= number <= 65535, whereas the IDMA2/ACPY2 specification required this to be either 1,2, or 4.
    numFrames. The number of frames in a block, 1 <= number <= 65535.
    SrcElementIndex and DstElementIndex. The offset in 8-bit bytes between the start addresses of two consecutive elements in a frame. Element indexes must be specified only when the source or destination is a 2D transfer. They are ignored for 1D transfers. Element indexes can be signed (i.e. negative) values in the range: -32767 <= number <= 32768.
    SrcFrameIndex and DstFrameIndex 1. The offset in 8-bit bytes between the start addresses of the first elements of two consecutive frames. (NOTE: This corresponds to the AB-synched SRC/DST CIDX settings in the EDMA3.0 DMA parameters.) Frame indexes must be specified only when the number of frames > 1, otherwise they are ignored. Frame indexes can be signed (negative or positive) values in the range: -32767 <= number <= 32768.
    numElements. The number of elements per frame, 1 <= number <= 65535.
    srcAddr and dstAddr. 8-bit byte-addresses.

Channel Privacy and Synchronization

Channel Privacy and Synchronization

Algorithms have exclusive ownership of each received logical channel and can operate safely without fear of external components (such as other algorithms or other system code) accessing the channel and issuing transfer requests or changing channel configuration settings. They must, however, follow the ACPY3 API to activate and deactivate each IDMA3 channel during instance activation and deactivation, respectively.

All synchronization calls are issued on a per channel basis, as opposed to a per transfer basis. An algorithm can issue either a blocking wait, or a non-blocking query call to synchronize with a logical channel’s completion status.

Tuesday, August 14, 2012

DSP chip’s important significance in our life

DSP chip’s important significance in our life

DSP also called digital siganal processor, it is a special structure of the microprocessor. The interior of DSP used the Harvard architecture that progarm and data separated, with special hardware multiplier, widely used in line operation, provide special DSP instructions, can be used to quickly achieve all kinds of digital siganl processing algorithms.

The modern science and technology product "heart" is chip, the DSP and the CPU is the two core technologies in the chip industry, the DSP for digital diganl processing, the CPU for computing capabilities.

DSP chip was widely used in many applications, such as the siganl processing, image processing, instrments, audio language, control, military, communication, medical, applicances.

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R8C family series MCU crack R5F212A crack

R8C family is a kind of 16-bit CISC MCU with high ROM effciency, low noise, low power consumption and high processing performance. Because it's rich timer function and various serial communication function built-in peripheral functions, the R8C Family apply to multiple applications. Mainly used in automotive electronics, audio equipment, home appliances, housing equipment (sensors, security systems), office equipment, industrial equipment.

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