CY8C20236A Evaluation Tools
All evaluation tools are sold at the Cypress Online Store.
CY3210-MiniProg1
The CY3210-MiniProg1 kit enables the user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
■ MiniProg Programming Unit
■ MiniEval Socket Programming and Evaluation Board
■ 28-Pin CY8C29466A-24PXI PDIP PSoC Device Sample
■ 28-Pin CY8C27443A-24PXI PDIP PSoC Device Sample
■ PSoC Designer Software CD
■ Getting Started Guide
■ USB 2.0 Cable
CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit
includes:
■ Evaluation Board with LCD Module
■ MiniProg Programming Unit
■ 28-Pin CY8C29466A-24PXI PDIP PSoC Device Sample (2)
■ PSoC Designer Software CD
■ Getting Started Guide
■ USB 2.0 Cable
CY3280-20x66 Universal CapSense Controller
The CY3280-20X66 CapSense Controller Kit is designed for
easy prototyping and debug of CY8C20xx6A CapSense Family
designs with pre-defined control circuitry and plug-in hardware.
Programming hardware and an I2C-to-USB bridge are included
for tuning and data acquisition.
The kit includes:
■ CY3280-20x66 CapSense Controller Board
■ CY3240-I2USB Bridge
■ CY3210 MiniProg1 Programmer
■ USB 2.0 Retractable Cable
■ CY3280-20x66 Kit CD
Device Programmers
All device programmers are purchased from the Cypress Online
Store.
CY3207ISSP In-System Serial Programmer (ISSP)
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production programming environment.
Note that CY3207ISSP needs special software and is not
compatible with PSoC Programmer. The kit includes:
■ CY3207 Programmer Unit
■ PSoC ISSP Software CD
■ 110 ~ 240 V Power Supply, Euro-Plug Adapter
■ USB 2.0 Cable
Friday, October 26, 2012
Thursday, October 18, 2012
CY7C09359AV-9AXC Code Extract
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Features
True dual ported memory cells which allow simultaneous
access of the same memory location
Two flow-through/pipelined devices
4 K × 18 organization (CY7C09349AV)
8 K × 18 organization (CY7C09359AV)
Three modes
Flow-through
Pipelined
Burst
Pipelined output mode on both ports allows fast 67-MHz
operation
0.35-micron complementary metal oxide semiconductor
(CMOS) for optimum speed/power
High-speed clock to data access 9 and 12 ns (max)
3.3 V low operating power
Active = 135 mA (typical)
Standby = 10 μA (typical)
Fully synchronous interface for easier operation
Burst counters increment addresses internally
Shorten cycle times
Minimize bus noise
Supported in flow-through and pipelined modes
Dual chip enables for easy depth expansion
Upper and lower byte controls for bus matching
Automatic power-down
Available in 100-pin thin quad flat pack (TQFP)
Features
True dual ported memory cells which allow simultaneous
access of the same memory location
Two flow-through/pipelined devices
4 K × 18 organization (CY7C09349AV)
8 K × 18 organization (CY7C09359AV)
Three modes
Flow-through
Pipelined
Burst
Pipelined output mode on both ports allows fast 67-MHz
operation
0.35-micron complementary metal oxide semiconductor
(CMOS) for optimum speed/power
High-speed clock to data access 9 and 12 ns (max)
3.3 V low operating power
Active = 135 mA (typical)
Standby = 10 μA (typical)
Fully synchronous interface for easier operation
Burst counters increment addresses internally
Shorten cycle times
Minimize bus noise
Supported in flow-through and pipelined modes
Dual chip enables for easy depth expansion
Upper and lower byte controls for bus matching
Automatic power-down
Available in 100-pin thin quad flat pack (TQFP)
CY7C09569V-100AXC Code Extract
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The CY7C09569V and CY7C09579V are high-speed 3.3 V
synchronous CMOS 16 K and 32 K × 36 dual-port static RAMs.
Two ports are provided, permitting independent, simultaneous
access for reads and writes to any location in memory. Registers
on control, address, and data lines allow for minimal set-up and
hold times. In pipelined output mode, data is registered for
decreased cycle time. Clock to data valid tCD2
= 5 ns (pipelined).
Flow-through mode can also be used to bypass the pipelined
output register to eliminate access latency. In flow-through mode
data will be available tCD1
= 12.5 ns after the address is clocked
into the device. Pipelined output or flow-through mode is
selected via the FT/Pipe pin.
Each port contains a burst counter on the input address register.
The internal write pulse width is independent of the external R/W
LOW duration. The internal write pulse is self-timed to allow the
shortest possible cycle times.
A HIGH on CE for one clock cycle will power down the internal
circuitry to reduce the static power consumption. In the pipelined
mode, one cycle is required with CE LOW to reactivate the
outputs.
Counter Enable Inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted, the
address counter will increment on each LOW-to-HIGH transition
of that port’s clock signal. This will read/write one word from/into
each successive address location until CNTEN is deasserted.
The counter can address the entire memory array and will loop
back to the start. Counter Reset (CNTRST) is used to reset the
burst counter.
Parts are available in 144-pin Thin Quad Plastic Flatpack
(TQFP), 144-pin Pb-free Thin Quad Plastic Flatpack (TQFP) and
172-ball Ball Grid Array (BGA) packages.
The CY7C09569V and CY7C09579V are high-speed 3.3 V
synchronous CMOS 16 K and 32 K × 36 dual-port static RAMs.
Two ports are provided, permitting independent, simultaneous
access for reads and writes to any location in memory. Registers
on control, address, and data lines allow for minimal set-up and
hold times. In pipelined output mode, data is registered for
decreased cycle time. Clock to data valid tCD2
= 5 ns (pipelined).
Flow-through mode can also be used to bypass the pipelined
output register to eliminate access latency. In flow-through mode
data will be available tCD1
= 12.5 ns after the address is clocked
into the device. Pipelined output or flow-through mode is
selected via the FT/Pipe pin.
Each port contains a burst counter on the input address register.
The internal write pulse width is independent of the external R/W
LOW duration. The internal write pulse is self-timed to allow the
shortest possible cycle times.
A HIGH on CE for one clock cycle will power down the internal
circuitry to reduce the static power consumption. In the pipelined
mode, one cycle is required with CE LOW to reactivate the
outputs.
Counter Enable Inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted, the
address counter will increment on each LOW-to-HIGH transition
of that port’s clock signal. This will read/write one word from/into
each successive address location until CNTEN is deasserted.
The counter can address the entire memory array and will loop
back to the start. Counter Reset (CNTRST) is used to reset the
burst counter.
Parts are available in 144-pin Thin Quad Plastic Flatpack
(TQFP), 144-pin Pb-free Thin Quad Plastic Flatpack (TQFP) and
172-ball Ball Grid Array (BGA) packages.
CY7C0851AV-167BBXC Code Extract
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The FLEx36? family includes 2M, 4M, and 9M pipelined,
synchronous, true dual-port static RAMs that are high-speed,
low-power 3.3 V CMOS. Two ports are provided, permitting
independent, simultaneous access to any location in memory.
The result of writing to the same location by more than one port
at the same time is undefined. Registers on control, address, and
data lines allow for minimal setup and hold time.
During a Read operation, data is registered for decreased cycle
time. Each port contains a burst counter on the input address
register. After externally loading the counter with the initial
address, the counter increments the address internally (more
details to follow). The internal Write pulse width is independent
of the duration of the R/W input signal. The internal Write pulse
is self-timed to allow the shortest possible cycle times.
A HIGH on CE0
or LOW on CE1
for one clock cycle powers down
the internal circuitry to reduce the static power consumption. One
cycle with chip enables asserted is required to reactivate the
outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
The CY7C0853V/CY7C0853AV device in this family has limited
features. Please see Address Counter and Mask Register
Operations on page 9 for details.
The FLEx36? family includes 2M, 4M, and 9M pipelined,
synchronous, true dual-port static RAMs that are high-speed,
low-power 3.3 V CMOS. Two ports are provided, permitting
independent, simultaneous access to any location in memory.
The result of writing to the same location by more than one port
at the same time is undefined. Registers on control, address, and
data lines allow for minimal setup and hold time.
During a Read operation, data is registered for decreased cycle
time. Each port contains a burst counter on the input address
register. After externally loading the counter with the initial
address, the counter increments the address internally (more
details to follow). The internal Write pulse width is independent
of the duration of the R/W input signal. The internal Write pulse
is self-timed to allow the shortest possible cycle times.
A HIGH on CE0
or LOW on CE1
for one clock cycle powers down
the internal circuitry to reduce the static power consumption. One
cycle with chip enables asserted is required to reactivate the
outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
The CY7C0853V/CY7C0853AV device in this family has limited
features. Please see Address Counter and Mask Register
Operations on page 9 for details.
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Features
True dual-ported memory cells that allow simultaneous access
of the same memory location
Synchronous pipelined operation
Organization of 2-Mbit, 4-Mbit, and 9-Mbit devices
Pipelined output mode allows fast operation
0.18-micron Complimentary metal oxide semiconductor
(CMOS) for optimum speed and power
High-speed clock to data access
3.3 V low power
Active as low as 225 mA (typ)
Standby as low as 55 mA (typ)
Mailbox function for message passing
Global master reset
Separate byte enables on both ports
Commercial and industrial temperature ranges
IEEE 1149.1-compatible Joint test action group (JTAG)
boundary scan
172-Ball fine-pitch ball grid array (FBGA) (1 mm pitch)
(15 mm × 15 mm)
176-Pin thin quad plastic flatpack (TQFP)
(24 mm × 24 mm × 1.4 mm)
Counter wrap around control
Internal mask register controls counter wrap-around
Counter-interrupt flags to indicate wrap-around
Memory block retransmit operation
Counter readback on address lines
Mask register readback on address lines
Dual chip enables on both ports for easy depth expansion
Features
True dual-ported memory cells that allow simultaneous access
of the same memory location
Synchronous pipelined operation
Organization of 2-Mbit, 4-Mbit, and 9-Mbit devices
Pipelined output mode allows fast operation
0.18-micron Complimentary metal oxide semiconductor
(CMOS) for optimum speed and power
High-speed clock to data access
3.3 V low power
Active as low as 225 mA (typ)
Standby as low as 55 mA (typ)
Mailbox function for message passing
Global master reset
Separate byte enables on both ports
Commercial and industrial temperature ranges
IEEE 1149.1-compatible Joint test action group (JTAG)
boundary scan
172-Ball fine-pitch ball grid array (FBGA) (1 mm pitch)
(15 mm × 15 mm)
176-Pin thin quad plastic flatpack (TQFP)
(24 mm × 24 mm × 1.4 mm)
Counter wrap around control
Internal mask register controls counter wrap-around
Counter-interrupt flags to indicate wrap-around
Memory block retransmit operation
Counter readback on address lines
Mask register readback on address lines
Dual chip enables on both ports for easy depth expansion
CY7C0853AV-100BBI Code Extract
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The FLEx36? family includes 2M, 4M, and 9M pipelined,
synchronous, true dual-port static RAMs that are high-speed,
low-power 3.3 V CMOS. Two ports are provided, permitting
independent, simultaneous access to any location in memory.
The result of writing to the same location by more than one port
at the same time is undefined. Registers on control, address, and
data lines allow for minimal setup and hold time.
During a Read operation, data is registered for decreased cycle
time. Each port contains a burst counter on the input address
register. After externally loading the counter with the initial
address, the counter increments the address internally (more
details to follow). The internal Write pulse width is independent
of the duration of the R/W input signal. The internal Write pulse
is self-timed to allow the shortest possible cycle times.
A HIGH on CE0
or LOW on CE1
for one clock cycle powers down
the internal circuitry to reduce the static power consumption. One
cycle with chip enables asserted is required to reactivate the
outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
The CY7C0853V/CY7C0853AV device in this family has limited
features. Please see Address Counter and Mask Register
Operations on page 9 for details.
The FLEx36? family includes 2M, 4M, and 9M pipelined,
synchronous, true dual-port static RAMs that are high-speed,
low-power 3.3 V CMOS. Two ports are provided, permitting
independent, simultaneous access to any location in memory.
The result of writing to the same location by more than one port
at the same time is undefined. Registers on control, address, and
data lines allow for minimal setup and hold time.
During a Read operation, data is registered for decreased cycle
time. Each port contains a burst counter on the input address
register. After externally loading the counter with the initial
address, the counter increments the address internally (more
details to follow). The internal Write pulse width is independent
of the duration of the R/W input signal. The internal Write pulse
is self-timed to allow the shortest possible cycle times.
A HIGH on CE0
or LOW on CE1
for one clock cycle powers down
the internal circuitry to reduce the static power consumption. One
cycle with chip enables asserted is required to reactivate the
outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
The CY7C0853V/CY7C0853AV device in this family has limited
features. Please see Address Counter and Mask Register
Operations on page 9 for details.
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Features
True Dual-Ported memory cells which enable simultaneous
access of the same memory location
Flow-through and Pipelined devices
32 K × 9 organizations (CY7C09179V)
64 K × 8 organizations (CY7C09089V)
128 K × 8/9 organizations (CY7C09099V/199V)
3 Modes
Flow-through
Pipelined
Burst
Pipelined output mode on both ports enables fast 100 MHz
operation
0.35-micron CMOS for optimum speed and power
High speed clock to data access 6.5
[1]
/7.5
[1]
/9/12 ns (max.)
3.3 V low operating power
Active = 115 mA (typical)
Standby = 10 ?A (typical)
Fully synchronous interface for easier operation
Burst counters increment addresses internally
Shorten cycle times
Minimize bus noise
Supported in Flow-through and Pipelined modes
Dual Chip Enables for easy depth expansion Automatic power down
Commercial and Industrial temperature ranges
Available in 100-pin TQFP
Pb-free packages available
Features
True Dual-Ported memory cells which enable simultaneous
access of the same memory location
Flow-through and Pipelined devices
32 K × 9 organizations (CY7C09179V)
64 K × 8 organizations (CY7C09089V)
128 K × 8/9 organizations (CY7C09099V/199V)
3 Modes
Flow-through
Pipelined
Burst
Pipelined output mode on both ports enables fast 100 MHz
operation
0.35-micron CMOS for optimum speed and power
High speed clock to data access 6.5
[1]
/7.5
[1]
/9/12 ns (max.)
3.3 V low operating power
Active = 115 mA (typical)
Standby = 10 ?A (typical)
Fully synchronous interface for easier operation
Burst counters increment addresses internally
Shorten cycle times
Minimize bus noise
Supported in Flow-through and Pipelined modes
Dual Chip Enables for easy depth expansion Automatic power down
Commercial and Industrial temperature ranges
Available in 100-pin TQFP
Pb-free packages available
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